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Kyungjun Min

M.S. - Ph. D. Student at POSTECH

Education

B.S. in Electrical Engineering

Pohang University of Science and Technology (POSTECH)
Feb.2016 - Feb.2021

M.S. - Ph.D. in Electrical Engineering

Pohang University of Science and Technology (POSTECH)
Feb.2021 - Current

Languages

  • Korean (Native)
  • English (Professional)

Interests

  • VLSI CAD
  • Physical Design
  • ML EDA
  • LLMs

About Theme

Career Profile

Kyungjun Min received a B.S. degree in electrical engineering from the Pohang University of Science and Technology (POSTECH), South Korea, in 2021. He is pursuing a Ph.D. degree in CAD & SoC Design Lab. at Pohang University of Science and Technology (POSTECH), South Korea. His current research interests include VLSI physical design optimization, AI-driven EDA and LLMs.

Experiences

Graduate Student Researcher

Feb.2021 - Current
CAD & SoC Design Lab(CSDL) in POSTECH, Prof, Seokhyeong Kang

Research Internship

July.2023 - Aug.2023
Design Technology Team, Memory Business in Samsung Electronics

Undergraduated Student Researcher

Sep.2020 - Feb.2021
CAD & SoC Design Lab(CSDL) in POSTECH, Prof, Seokhyeong Kang

Undergraduated Student Researcher

Jan.2019 - Feb.2019
CAD & SoC Design Lab(CSDL) in POSTECH, Prof, Seokhyeong Kang

Research Internship

Jun.2018 - Aug.2018
DEMO

Research Internship

July.2017 - Aug.2017
POSCO DX

Projects

Wafer-Scale Physics Modeling – ISPD Contest
AI Semiconductor Design Software Development – National Research Foundation of Korea
Virtual Netlist Development Considering Standard Cell Usage – Samsung Electronics
Functional ECO with Behavioral Change Guidance – ICCAD Contest
Research on Physical Design (Place & Route) Optimization – Samsung Electronics
Machine Learning Based Electronic Design Automation Software Development – Samsung Electronics
Artificial Design Generation using Generative AI Models – Samsung Electronics
LLM-Assisted Hardware Code Generation – ICCAD Contest
AI-based IC Design Techniques – LX Semicon
(2nd Prize) ReSynthAI: Physical-Aware Logic Resynthesis for Timing Optimization Using AI - MLCAD Contest

Publications

  • (Co-Author) Signal-Integrity-Aware Interposer Bus Routing in 2.5D Heterogeneous Integration
    • IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC 2022)
  • (Co-Author) CTRL-B: Back-End-Of-Line Configuration Pathfinding using Cross-Technology Transferable Reinforcement Learning
    • IEEE/ACM Design, Automation and Test in Europe Conference and Exhibition (DATE 2023)
  • (Co-Author) Construction of Realistic Place-and-route Benchmarks for Machine Learning Applications
    • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD 2023)
  • (1st Author) ClusterNet: Routing Congestion Prediction and Optimization using Netlist Clustering and Graph Neural Networks
    • IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2023)
  • (1st Author) PPA-Relevant Clustering-Driven Placement for Large-Scale VLSI Designs
    • ACM/IEEE Design Automation Conference (DAC 2024)
  • (Co-Author) VeriLogos: Automatic Verilog RTL Generation using Large Language Models
    • International SoC Design Conference (ISOCC 2024)
  • (1st Author) Leveraging Machine Learning Techniques for Traditional EDA Workflow Enhancement
    • IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC 2025)
  • (1st Author) Improving LLM-based Verilog Code Generation with Data Augmentation and RL
    • IEEE/ACM Design, Automation and Test in Europe Conference and Exhibition (DATE 2025)
  • (1st Author) REvolution: An Evolutionary Framework for RTL Generation driven by Large Language Models
    • IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC 2026))